This invention relates to the field of control signal interface circuits with improved rise and fall time and low capacitive loading.
Since the development of the personal computer, the characteristics and performance of the main memory has played a major role in defining the capabilities of the computers. From the beginning, the trend in the state of the art has been toward larger, faster main memory that is simultaneously consistent with the trend to ever-lower computer prices. One aspect of main memory is the need for a control signal for use with the memory.
In the present art, a typical control signal is coupled through a series resistor (22 ohms) to one or more memory devices (e.g. eight or nine memory devices) through transmission line structures (typically having a characteristic impedance of, for example, 60-65 ohms). The form of memory device interconnection frequently depends on the location of the input signal pin on the DIMM, with daisy-chain connections very common. At best, the present art loads the input control signal with the equivalent input capacitance of each of the memory devices input pins (typically 3-5 pf each) in parallel. The total capacitance has made it extremely difficult to achieve fast memory speeds. In fact, the control-signal rise and fall times are typically greater than the entire clock period, forcing increased latency and effectively limiting memory access speeds.
It may be observed that where memory clock speeds were once comparable to processor clock speeds, at present they are only about one tenth of that of the processor without even considering the impact of latency. As a result, it would be desirable to have a memory interface circuit which simultaneously provides for fast rise and fall times, consistent faster timing, low capacitive loading on the motherboard, the ability to add multiple banks of memory devices without increasing capacitive loading, and the ability to parallel multiple memory modules on the memory bus without significantly impacting performance.